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What Do We Do With 10^12 Transistors? The Case For Precision Timing

Google Tech TalksFebruary, 21 2008ABSTRACTIt is will be too costly to design many of these chips at the polygonor even gate level, so they must be highly programmable. Furthermore,they should not just be FPGAs as we now know them because with thatmany transistors, we should specialize more for power efficiency. Ienvision FPGA-like chips where the computational elements combine CPUswith more traditional FPGA-like fabrics.For embedded real-time applications, which I argue will dominate, Iargue that the temporal behavior of these processors should be as easyto analyze and control as their functional behavior.I present a vision such a precision-timed (PRET) processor, whichincorporates a variety of techniques. At the ISA level, it providescycle-accurate timers, a predictable memory hierarchy based onscratchpad memories, and an interleaved pipeline that providespredictable, hardware-efficient concurrency. It will be programmed ina C-like language that includes user-specified timing constraints andconcurrency, perhaps with synchronous semantics. Both compile- andrun-time checks will ensure the program meets timing constraints,similar to array bounds checking.Speaker: Stephen A. EdwardsStephen A. Edwards received the B.S. degree in Electrical Engineeringfrom the California Institute of Technology in 1992, and the M.S. andPh.D degrees, also in Electrical Engineering, from the University ofCalifornia, Berkeley in 1994 and 1997 respectively. He is currentlyan associate professor in the Computer Science Department of ColumbiaUniversity in New York, which he joined in 2001 after a three-yearstint with Synopsys, Inc., in Mountain View, California. His researchinterests include embedded system design, domain-specific languages,and compilers.
Length: 51:30


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