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Recognizing Opportunities for Thread Level Parallelism...

Google Tech TalksMarch 15, 2007ABSTRACTWith the rise of chip-multiprocessors (CMPs) as the high-performance architecture of choice, programmers must now find and extract parallelism from their applications to see continued performance improvements. Previous analysis of long-running non-scientific (e.g., SPECint like) program trace data has shown that a fair amount of parallelism is present in modern sequential applications, but this parallelism cannot be exploited via the classic instruction-level parallel approach. Despite the promise of extracting this parallelism for CMPs, no work characterizes which code sequences are parallelizable because these large traces (e.g., terabytes in size,...
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